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19-1469; Rev 0; 7/99
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
General Description
The MAX5165 contains four 1-to-8 multiplexers and 32 sample/hold amplifiers. A single analog input connects to all four internal 1-to-8 multiplexers. The sample/hold amplifiers are organized into four octal sample/holds with independent TTL/CMOS-compatible track/hold enables for each octal set. Additional 3-bit TTL/CMOScompatible address logic selects the 1-to-8 multiplexer channel. Clamping diodes on each output allow clamping between two external reference voltages. The MAX5165 is available with an output impedance of 50, 500, or 1k, allowing output filtering. The MAX5165 operates with +10V and -5V supplies and a separate +5V digital logic supply. Manufactured with a proprietary BiCMOS process, it provides high accuracy, fast acquisition time, low droop rate, and a low hold step. The device acquires 8V step input signals to 0.01% accuracy in 2.5s. Transitions from sample mode to hold mode result in only a 0.5mV error. While in hold mode, the output voltage slowly droops at a rate of 1mV/sec. The MAX5165 is available in a 48-pin TQFP package. o 32-Channel Sample/Hold o Output Clamping o 0.01% Accuracy of Acquired Signal o 0.01% Linearity Error o Fast Acquisition Time: 2.5s o Low Droop Rate: 1mV/sec o Low Hold Step: 0.25mV o Wide Output Voltage Range: +7V to -4V
Features
MAX5165
Ordering Information
PART MAX5165LCCM TEMP. RANGE 0C to +70C PINPACKAGE 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP ROUT () 50 500 1k 50 500 1k
Applications
Automatic Test Equipment (ATE) Industrial Process Controls Arbitrary Function Generators Avionics Equipment
MAX5165MCCM 0C to +70C MAX5165NCCM 0C to +70C MAX5165LECM -40C to +85C MAX5165MECM -40C to +85C MAX5165NECM -40C to +85C
Pin Configuration
A1 A0 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22
48 47 46 45 44 43 42 41 40 39 38 37
A2 M0 M1 M2 M3 VL DGND VSS AGND IN CH CL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 VDD OUT15 OUT14 OUT13 OUT12 OUT11
MAX5165
________________________________________________________________ Maxim Integrated Products
N.C. OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10
TQFP 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
ABSOLUTE MAXIMUM RATINGS
VDD to AGND.......................................................-0.3V to +11.0V VSS to AGND .........................................................-6.0V to +0.3V VDD to VSS ......................................................................+15.75V VL to DGND...........................................................-0.3V to +6.0V VL to AGND ...........................................................-0.3V to +6.0V DGND to AGND.....................................................-0.3V to +2.0V IN to AGND .................................................................VSS to VDD A_, M_ to DGND ....................................................-0.3V to +6.0V CH, CL to AGND .................................................-6.0V to +11.0V Maximum Current into Output Pin ....................................10mA Maximum Current into A_, M_ ..........................................20mA Continuous Power Dissipation (TA = +70C) 48-pin TQFP (derate 12.5mW/C above +70C).........1000mW Operating Temperature Ranges MAX5165_CCM ...................................................0C to +70C MAX5165_ECM.................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C Maximum Current into CH, CL, PIN..................................80mA
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +10V, VSS = -5V, VL = +5V 5%, AGND = DGND, RL = 5k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ANALOG SECTION Linearity Error Hold Step Droop Rate Offset Voltage Output Voltage Range VHS VOUT_ VOS VOUT_ -4V < VIN < +7V, RL = IN = AGND IN = AGND, TA = +25C IN = AGND, TA = +25C +15C TA +65C (Note 1) RL = 8V step with 500ns rising edge (Note 1) CIN MAX5165L DC Output Impedance Output Source Current Output Sink Current Output Clamp High Output Clamp Low TIMING PERFORMANCE 8V step to 0.08%, RL = , Figure 2 (Note 2) Acquisition Time Hold-Mode Settling Time Aperture Delay Inhibit Pulse Width Data Hold Time Data Setup Time 2 tAQ tH tAP tPW tDH tDS TA = +25C, 100mV step to 1mV, RL = , Figure 2 (Note 2) To 1mV of final value, Figure 2 (Note 1) Figure 2 (Note 1) Figure 2 (Note 1) Figure 2 (Note 1) Figure 2 (Note 1) 200 150 50 2.5 1 1 2 200 4 s s ns ns ns ns ROUT_ ISOURCE ISINK VCH VCL RL = , CL = 250pF MAX5165M MAX5165N 35 350 700 2 2 VSS VSS VDD VDD MAX5165L, CL = 250pF MAX5165M, CL = 10nF MAX5165N, CL = 10nF VSS + 0.75 -72 -72 -72 -76 -76 -76 10 50 500 1000 20 65 650 1300 mA mA V V pF dB -30 0.01 0.25 1 -5 20 0.08 1.00 40 30 40 VDD 2.4 % mV mV/sec mV V/C V SYMBOL CONDITIONS MIN TYP MAX UNITS
Analog Crosstalk Input Capacitance
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -5V, VL = +5V 5%, AGND = DGND, RL = 5k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DIGITAL INPUTS Input Voltage High Input Voltage Low Input Current POWER SUPPLIES Positive Analog Supply Voltage Negative Analog Supply Voltage Digital Logic Supply Voltage Positive Analog Supply Current Negative Analog Supply Current Digital Logic Supply Current Digital Logic Supply Current Power-Supply Rejection Ratio VDD VSS VL IDD ISS IL IL PSRR RL = RL = A0-A3 = DGND or VL; M0, M1, M2 = DGND or VCC A0-A3 = 0.8V or 2V; M0, M1, M2 = 0.8V or 2V For both VDD and VSS in sample mode, VIN = 0 -60 -75 (Note 3) (Note 3) 9.5 -4.75 4.75 10 -5.0 5 10.5 -5.45 5.25 36 36 0.5 5 V V V mA mA mA mA dB VIH VIL II A_ = DGND or VL, M_ = DGND or VL -1 2.0 0.8 +1 V V A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5165
Note 1: Guaranteed by design. Note 2: Only one M_ input may be asserted low at a time, so only one channel is selected (see Single vs. Simultaneous Sampling). Note 3: Do not exceed the absolute maximum rating for VDD to VSS of +15.75V (see Absolute Maximum Ratings).
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
Typical Operating Characteristics
(VDD = +10V, VSS = -5V, VL = +5V, IN = GND, RL = , CL = 0, AGND = DGND, VCH = VDD, VCL = VSS, TA = +25C, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO (HOLD MODE)
MAX5165-06
DROOP RATE vs. TEMPERATURE
MAX5165-01
DROOP RATE vs. INPUT VOLTAGE
1.50 1.45 1.40 DROOP RATE (mV/sec) 1.35 PSRR (dB) 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -5.0 -3.5 -2.0 -0.5 1.0 2.5 4.0 5.5 7.0 8.5 10.0 INPUT VOLTAGE (V) 1
16 14 DROOP RATE (mV/sec) 12 10 8 6 4 2 0 -40 -20 0 20 40 60 80
-SUPPLY
+SUPPLY
100
10
100 FREQUENCY (kHz)
1k
10k
TEMPERATURE (C)
POWER-SUPPLY REJECTION RATIO (SAMPLE MODE)
MAX5165-03
HOLD STEP vs. TEMPERATURE
MAX5165-04
HOLD STEP vs. INPUT VOLTAGE
90 80
MAX5165-07
-90 -80 -70
75
100
HOLD STEP (V)
HOLD STEP (V)
-60 PSRR (dB) -50 -40 -30 -20 -10 0 1 10 100 FREQUENCY (kHz) -SUPPLY
+SUPPLY
50
70 60 50 40 30 20 10
25
0 1k 10k -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
0 -5.0 -3.0 -1.0 1.0 3.0 5.0 7.0 INPUT VOLTAGE (V)
OFFSET VOLTAGE vs. TEMPERATURE
MAX5165-05
OFFSET VOLTAGE vs. INPUT VOLTAGE
-3.6 -3.7 OFFSET VOLTAGE (mV) -3.8 -3.9 -4.0 -4.1 -4.2 -4.3 -4.4
MAX5165-08
-2.0 -2.5 OFFSET VOLTAGE (mV) -3.0 -3.5 -4.0 -4.5 -5.0 -40 -20 0 20 40 60 80
-3.5
-4.5 100 -5.0 -3.0 -1.0 1.0 3.0 5.0 7.0 TEMPERATURE (C) INPUT VOLTAGE (V)
4
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MAX5165-02
18
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
M2 M1 M3 M0 A2 A1 A0 CH CL D0 D0 D31 AND7 OUTPUT CLAMPING EN OUT0 D31
MAX5165
3-TO-8 DECODER
8
8
1-TO-8 MULTIPLEXER AND0
IN SAMPLE-AND-HOLD 8 1-TO-8 MULTIPLEXER
OUT7
OUT8 EN IN SAMPLE-AND-HOLD IN 8 1-TO-8 MULTIPLEXER OUT16 EN IN SAMPLE-AND-HOLD 8 1-TO-8 MULTIPLEXER OUT24 EN IN SAMPLE-AND-HOLD DGND AGND VCC VDD VL OUT31 OUT23 OUT15
Figure 1. Functional Diagram
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
Pin Description
PIN 1, 47, 48 NAME A2, A0, A1 FUNCTION Address Inputs. The input of a 3-to-8 decoder, which controls channel selection for all four 1-to-8 multiplexers simultaneously. Selects which output channels are connected to the input during sample mode (Tables 1, 2). Mode-Selection/Multiplexer-Enable Inputs 0 to 3. Independent controls for each of the four 1-to-8 multiplexers. A logic low enables sample mode by connecting the selected channel (via address inputs A2, A1, A0) to IN. A logic high selects hold mode (Tables 1, 2). Positive Digital Logic Power-Supply Input Digital Ground Negative Analog Power-Supply Input Analog Ground Analog Input. Connects to the input of all four internal 1-to-8 multiplexers. Clamp High Input. Clamps VOUT to (VCH + 0.7V). Clamp Low Input. Clamps VOUT to (VCL - 0.7V). No Connection. Not internally connected. Sample/Hold Outputs 0 to 15 Positive Analog Power-Supply Input Sample/Hold Outputs 16 to 31
2-5 6 7 8 9 10 11 12 13 14-29 30 31-46
M0-M3 VL DGND VSS AGND IN CH CL N.C. OUT0-OUT15 VDD OUT16-OUT31
_______________Detailed Description
The MAX5165 connects a single analog input to the inputs of four internal 1-to-8 analog multiplexers. Each multiplexer channel connects to a buffered sample/hold circuit and a series output resistor, creating a singleinput device with 32 sample/hold output channels. Three multiplexer channel-address inputs and four mode-select inputs (one for each multiplexer) control channel selection and sample/hold functions (Figure 1 and Tables 1, 2).
Sample/Hold
The MAX5165 contains 32 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The value of the hold capacitor affects acquisition time and droop rate. Lower capacitance allows faster acquisition times but increases the droop rate. Higher values increase hold time and acquisition time. The hold capacitor used in the MAX5165 provides fast 2.5s (typ) acquisition time while maintaining a low 1mV/sec (typ) droop rate, making the sample/hold ideal for high-speed sampling.
Digital Interface
Three address pins and 3-to-8 address decoder logic select the channel for all four internal analog multiplexers. The mode-select inputs (M3-M0) independently control the sample/hold functions for each multiplexer (Tables 1, 2).
6
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
Table 1. Output Selection
ADDRESS A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 MUX0 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUTPUT SELECTED MUX1 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 MUX2 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 MUX3 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31
0 = Logic Low, 1 = Logic High
Table 2. Mode Selection
MODE-SELECT INPUTS (M3-M0) 0 ACTION Sample mode enabled on selected analog multiplexer and channel (Table 1). Hold mode enabled on selected analog multiplexer and channel (Table 1).
Hold Step When switching between sample mode and hold mode, the voltage of the hold capacitor changes due to charge injection from stray capacitance. This voltage change, called hold step, is minimized by limiting the amount of stray capacitance seen by the hold capacitor. The MAX5165 limits the hold step to 0.25mV (typ). An output capacitor to ground can be used to filter out this small hold-step error.
1
Output
The MAX5165 contains an output buffer for each multiplexer channel (32 total), so the hold capacitor sees a high-impedance input, reducing the droop rate. The capacitor droops at a 1mV/sec (typ) rate while in hold mode. The buffer also provides a low output impedance; however, the device contains output resistors in series with the buffer output (Figure 1) for selected output filtering. To provide greater design flexibility, the MAX5165 is available with an RO of 50, 500, or 1k. Note: Output loads increase the analog supply current (IDD and ISS). Excessive loading of the output(s) damages the device by consuming more power than the device will dissipate (see Absolute Maximum Ratings). The resistor-divider formed by the output resistor (ROUT) and load impedance (RL) scales the sampled voltage (VSAMP). Determine the output voltage (VOUT_) as follows: Voltage Gain = AV = RL / (RL + ROUT) VOUT_ = VSAMP * AV The maximum output voltage range depends on the analog supply voltages available, and the scaling factor used: (VSS + 0.75V) * AV VOUT_ (VDD - 2.4V) * AV when RL = , then AV = 1 and this equation becomes: (VSS + 0.75V) VOUT (VDD - 2.4V)
0 = Logic Low, 1 = Logic High * Only one M_ input asserted low; all others must be logic high to meet the timing specification (see Single vs. Simultaneous Sampling section).
Sample Mode Driving M3-M0 low (one at a time) selects sample mode (Tables 1, 2). During sample mode, the selected multiplexer channel connects to IN, allowing the hold capacitor to acquire the input signal. To guarantee an accurate sample, maintain sample mode for at least 4s. The output of the S/H amplifier tracks the input after 4s. Only the addressed channel on the selected multiplexer samples the input; all other channels remain in hold mode. Hold Mode Driving M3-M0 high selects hold mode. Hold mode disables the multiplexer and disconnects all eight channels on the 1-to-8 multiplexer from the input. When a channel is disconnected, the hold capacitor maintains the sampled voltage at the output with a 1mV/sec droop rate (towards VDD).
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7
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
Output Clamp
The MAX5165 clamps the output between two externally applied reference voltages. Internal diodes connect all outputs to the clamping voltages, restricting the output voltage to: VCH + 0.7V VOUT_ VCL - 0.7V When the clamping voltage exceeds the maximum output voltage, the maximum output voltage will be the limiting factor. To disable output clamping, connect CH to VDD and CL to VSS to set the clamping voltages beyond the maximum output voltage range. The clamping diodes allow the MAX5165 to be used with other devices requiring restricted input voltages.
__________Applications Information
Control-Line Reduction
The MAX5165 contains four separate 1-to-8 multiplexers and individual mode selectors for each multiplexer. Configure the device to sample only one channel at a time or up to four channels (with the same address, see Table 1) simultaneously. When sampling one channel at a time, use an external 2-to-4 decoder (with activelow outputs) to reduce the number of digital control lines from seven to five (Figure 3).
Single vs. Simultaneous Sampling
Individually control the four mode/multiplexer-select pins to simultaneously sample on four channels, the same channel for each multiplexer (Figure 4). Each mode-select pin controls sampling on one of the 1-to-8 multiplexers, while the 3-bit address selects one of the eight channels on all the multiplexers (Tables 1, 2). Setting any combination of the mode-select pins low enables sampling on the addressed channels for the selected multiplexers. Simultaneously sampling two or more channels reduces offset voltage but increases acquisition time. Multiply the single-channel acquisition time by the number of channels sampling.
Timing Definitions
Acquisition time (t AQ ) is the amount of time the MAX5165 must remain in sample mode for the hold capacitor to acquire an accurate sample. The holdmode settling time (tH) is the amount of time necessary for the output voltage to settle to its final value. Aperture delay (tAP) is the time interval required to disconnect the input from the hold capacitor. The inhibit pulse width (tPW) is the amount of time the MAX5165 must remain in hold mode while the address is changed. The data setup time (tDS) is the amount of time an address must be maintained before the address becomes valid. The data hold time (tDH) is the amount of time that an address must be maintained after mode select has gone from low to high (Figure 2).
tPW MODE SELECT
tDS ADDRESS (A0-A2) tDH OUTPUT tH HOLD STEP
INPUT
tAQ
tAP
Figure 2. Timing Performance 8 _______________________________________________________________________________________
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
1/16 MAX5165 A0-A2 3 ADDRESS DECODER 2 MODE SELECTOR DECODER M0 M1 M2 M3
CHANNEL ADDRESS
5
3
OUT0
AGND INPUT SIGNAL IN OUT8
AGND
Figure 3. Control-Line Reduction
ADDRESS
3
1/16 MAX5165 A0-A2 3 ADDRESS DECODER M0 M1 M2 M3
MODE/MULTIPLEXER SELECTION
OUT0
AGND INPUT SIGNAL IN OUT8
AGND
Figure 4. Simultaneous Sampling _______________________________________________________________________________________ 9
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
Multiplexed DAC
Figure 5 shows a typical demultiplexer application. Different digital codes are converted by the digital-toanalog converter (DAC) and then stored on 32 different channels of the MAX5165. The 100mV/sec (max) droop rate requires refreshing the hold capacitors every 100ms before the voltage drops by 1/2LSB for an 8-bit DAC with a 5V full-scale voltage.
Powering the MAX5165
The MAX5165 does not require a special power-up sequence to avoid latchup. The device requires three separate supply voltages for operation; however, when one or two of the voltages are not available, DC-DC charge-pump (switched-capacitor) converters provide a simple, efficient solution. The MAX860 provides voltage doubling or inversion, ideal for conversions from +5V to +10V or from +5V to -5V. The MAX860 also functions as a voltage divider to provide conversion from +10V to +5V.
ADDRESS
5
3
1/16 MAX5165 A0-A2 3 ADDRESS DECODER
2 MODE SELECTOR DECODER
M0 M1 M2 M3
OUT0
AGND DIGITAL INPUTS DAC IN OUT8
AGND
Figure 5. Multiplexing a DAC
Chip Information
TRANSISTOR COUNT: 5077
10
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
Package Information
TQFPPO.EPS
MAX5165
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5165
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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